P H 4 4 0 N L X M o t h e r b o a r d U s e r G u i d e
The major busses (processor, memory, PCI and AGP) all operate independently to achieve a
high degree of concurrency. Most CPU-DRAM and AGP-DRAM transfers can occur
concurrently with PCI transfers and so consume no PCI bus bandwidth.
LEVEL 2 CACHE
The second level cache is contained within the processor module. There is no provision for a
third level cache.
Cache size is determined by the type of CPU fitted, refer to your CPU manufacturer for this
There is no main memory fitted directly to the motherboard.
There are three DIMM sockets on the motherboards that accept 168-pin un-buffered SDRAM
modules to the PC100 memory module specification. All modules must support SPD (serial
presence detect) to allow the BIOS to determine the memory configuration and set up the chipset
optimally. These modules contain a small EEPROM that describes the module capabilities in
detail - including speed, capacity and organisation.
64-bit or 72-bit (ECC) modules.
2 or 4 bank organisation
Asymmetric or symmetric memory addressing.
Single or double-sided modules.
The BIOS is contained in a flash ROM device soldered directly to the motherboard and includes
the code listed below. The motherboard will automatically perform a BIOS recovery operation if
it detects a valid recovery disk during the boot sequence. An override jumper that prevents all
writes (recovery or update) provides update protection. The BIOS ROM is accessed as a single
linear region in the memory space from 4GB-128kB (0FFFE0000 - 0FFFFFFFFh) and copied at
the top of ISA memory (0E0000 - 0FFFFFh).
Core motherboard BIOS
VGA BIOS (ATI RAGE PRO or RAGE IIC)
USB, including legacy support
Intel Pentium II
Power and system management code
There is no support for configuration RAM other than the CMOS RAM within the RTC.
MITSUBISHI ELECTRIC MOTHERBOARD DIVISION
microcode update support and code
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